How many vector memory locations are reserved for each restart instruction in the 8085 vector interrupt table?
Vector addresses in 8085 are spaced 8 bytes apart (e.g., RST 0 at 0000H, RST 1 at 0008H, RST 2 at 0010H, etc.), providing 8 bytes of space for a short jump instruction to the full ISR.
In an automated factory system, a temperature sensor triggers a hardware interrupt. What is the advantage of using vectored interrupts over non-vectored interrupts?
Vectored interrupts eliminate the software polling latency needed to identify the interrupting device, reducing interrupt response time.
What is precise interrupt handling in a pipelined processor?
Precise interrupts ensure that when an exception occurs, all instructions prior to the faulting instruction in program order have fully committed, while the faulting instruction and later instructions leave no modified CPU state.
In x86, when a maskable hardware interrupt is delivered through an interrupt gate, what happens to the IF flag on entry to the handler?
For an x86 interrupt gate, hardware clears IF on entry, disabling maskable interrupts until software re-enables them. A trap gate differs because it does not clear IF automatically.
In x86 architecture, how many total entries exist in the Interrupt Vector Table (IVT) or Interrupt Descriptor Table (IDT)?
x86 supports an 8-bit interrupt vector number, yielding $2^8$ = 256 vector entries in the IVT/IDT.