In the 8085 microprocessor, what is the vector address in hexadecimal for the TRAP interrupt?
The 8085 TRAP interrupt uses vector address 0024H. It is the highest-priority hardware interrupt and is non-maskable; it should not be described as an RST 4.5 instruction.
Which of the following conditions must be satisfied for the CPU to service a maskable hardware interrupt?
Servicing a maskable interrupt requires both global interrupt enable (EI instruction / IF = 1) and local unmasking of the designated interrupt bit.
In Software Polling priority scheme for handling multiple interrupts, how is priority enforced?
When an interrupt occurs, the CPU executes a polling routine that tests device status flags in order. The device tested first has highest priority.
What is Nested Interrupt handling?
Nested interrupts permit a higher-priority hardware request to temporarily suspend a running lower-priority ISR, ensuring real-time responsiveness.
Which type of instruction is used at the end of an Interrupt Service Routine (ISR) to restore the saved interrupt context and resume the interrupted program?
Architecture-specific interrupt-return instructions such as IRET or RETI restore the required saved interrupt context and return control to the interrupted program.