What is the purpose of the Address Latch Enable (ALE) signal in multiplexed address/data bus architectures (e.g., Intel 8085)?
ALE goes HIGH during the first clock period T1 of a machine cycle to signal that AD0-AD7 contain valid address bits, which are latched externally so the lines can carry data in subsequent T-states.
In a memory-mapped I/O system with a 32-bit address bus, if full-address decoding is required to select exactly one I/O address, how many address bits must the decoder examine?
With full-address decoding, all 32 address bits are examined so that the specified 32-bit address can be uniquely selected.
Which bus arbitration approach uses a single central hardware controller to grant bus access to requesting master devices?
Centralized arbitration relies on a single dedicated bus arbiter chip to receive Bus Requests and issue Bus Grants to competing bus masters.
In a common distributed bus-arbitration scheme, how can competing masters determine which requester has the highest priority?
In a common self-selection distributed arbitration scheme, each requesting master places its priority code on shared arbitration lines and determines whether it has the highest-priority active request.
In a 1-cycle bus transfer protocol, if bus clock period is 10 ns and data bus width is 64 bits, what is the maximum theoretical bus throughput?
$64 bits = 8 bytes per 10 ns clock cycle. Rate = 8 bytes / 10 ns = 8 B / 10^{-8} s = 800 MB/s.$