Question 76
For a JK flip-flop, the required inputs for the transition $Q=0$ to Q_next=1 are:
Detailed Solution
The JK excitation condition for 0→1 is $J=1$ and $K=X$.
✓ Saved
GATE CSE Digital Logic – Full Comprehensive Mixed Mock Test-1
Your score
0/100
0 answered
Correct 0
Incorrect 0
Unanswered 100
Accuracy 0%
Question 77
Hold time of a flip-flop is:
Detailed Solution
Hold time is the minimum duration after the clock transition during which input data must not change.
✓ Saved
Question 78
Metastability in digital circuits is caused by:
Detailed Solution
When asynchronous inputs change within setup/hold window, flip-flop enters an unstable metastable state.
✓ Saved
Question 79
A conventional master-slave D flip-flop consists of how many cascaded latch stages?
Detailed Solution
It consists of a master latch followed by a slave latch.
✓ Saved
Question 80
How many clock pulses are required to serially load an 8-bit word into an 8-bit SIPO shift register?
Detailed Solution
One bit is shifted in per clock, so 8 bits require 8 clock pulses.
✓ Saved