Question 71
An SR latch built with NOR gates has invalid state when:
Detailed Solution
For NOR SR latch, $S=1$, $R=1 forces both Q$ and Q' to 0, which is invalid.
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GATE CSE Digital Logic – Full Comprehensive Mixed Mock Test-1
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Question 72
An SR latch built with NAND gates has invalid state when:
Detailed Solution
For active-LOW NAND SR latch, S'=0, R'=0 forces both Q and Q' to 1, which is invalid.
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Question 73
A D flip-flop has $Q=1$. If $D=0$ is applied at the active clock edge, what is the new Q?
Detailed Solution
A D flip-flop transfers D to Q on the active clock edge.
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Question 74
Excitation table of a flip-flop specifies:
Detailed Solution
Excitation table lists required flip-flop inputs (J,K or D or T) for transition from Q_present to Q_next.
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Question 75
For a JK flip-flop, which input condition is sufficient for the transition $Q=1$ to Q_next=1?
Detailed Solution
For a JK flip-flop, the excitation condition for 1→1 is $J=X$ and $K=0$; J may be either 0 or 1 while K must be 0.
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