How can an SR flip-flop be converted into a D flip-flop?
By setting $S = D$ and R = D', when $D=1$, $S=1,R=0 (SET)$; when $D=0$, $S=0,R=1 (RESET)$.
For a JK flip-flop, the required inputs for the transition $Q=1$ to Q_next=0 are:
From the JK excitation table, 1→0 requires $K=1 while J$ is don't-care.
Which of the following conditions correctly prevent a hold-time violation in a synchronous circuit, assuming clock skew is defined as t_capture - t_launch?
Hold timing is governed by the minimum path delay: t_clk-q(min)+$t_{cd}$(min) must be at least t_hold+t_skew under the stated skew convention. Increasing the clock period does not by itself fix a hold violation.
In a conventional positive-level master-slave JK flip-flop in which the master latch is enabled when CLK=1, the master is active during:
In this stated master-slave implementation, the master is transparent during CLK=1 and the slave during CLK=0.
A T flip-flop has Q_next=T⊕Q and T=A$\cdot Q'$. If $A=1$ and $Q=0$, what is Q_next?
T=1$\cdot 0'=1$, hence Q_next=1⊕0=1.