GATE CSE Digital Logic – Full Comprehensive Mixed Mock Test-1 ⋆ CSE Study247

GATE CSE Digital Logic – Full Comprehensive Mixed Mock Test-1

Questions 61-65 of 100

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Question 61

MCQ · Single Correct 1 mark

The characteristic equation of a JK flip-flop is:

A Q_next = J + K' Q B Q_next = J Q' + K' Q C Q_next = J' Q' + K Q D Q_next = J Q + K Q'

Question 62

MCQ · Single Correct 1 mark

A T flip-flop has $T=1$ and starts with $Q=0$. What is Q after 7 active clock pulses?

A Undefined B 0 C 1 D Depends on setup time

Question 63

MCQ · Single Correct 1 mark

Race-around condition in a level-triggered JK flip-flop occurs when:

A $J=0$, $K=1$, with an edge-triggered clock B $J=1$, $K=0$, with a level-triggered clock C $J=1$, $K=1$, and the active clock pulse width exceeds the flip-flop propagation delay D $J=0$, $K=0$, with an edge-triggered clock

Question 64

MSQ · Multiple Correct 1 mark

Which statements are CORRECT for the timing parameters t_setup=3 ns, t_hold=2 ns, $t_{pd}$=5 ns, and t_comb=10 ns?

A The minimum clock period is 18 ns. B The hold time changes the computed minimum period in the given setup-only calculation. C The maximum clock frequency is approximately 55.56 MHz. D The setup-time constraint includes $t_{pd}$, t_comb, and t_setup.

Question 65

MCQ · Single Correct 1 mark

Using $t_{pd}$=5 ns, t_comb=10 ns, t_setup=3 ns, what is the maximum clock frequency?

A 55.56 MHz B 50 MHz C 62.5 MHz D 18 MHz