A memory interleaving scheme uses 4 banks with low-order interleaving. Which bank holds address 6?
Low-order interleaving bank index = Address mod Number of banks = 6 mod 4 = Bank 2.
What type of cache miss occurs on the very first access to a memory block?
Compulsory misses occur when a block is referenced for the first time.
In an inclusive multi-level cache policy (L1 and L2), what condition must hold?
Inclusive cache policy guarantees that L2 contains a complete superset of L1 data.
A 128 KB direct-mapped cache has 32-byte blocks. How many cache lines does it contain?
$Lines = 128 KB / 32 B = (128 * 1024) / 32 = 4096 lines.$
What hardware buffer prevents the CPU from stalling on write operations in a Write-Through cache?
A Write Buffer temporarily holds written data so the CPU can resume execution immediately while writes complete to memory.