In Memory-Mapped I/O, how are I/O ports addressed by the CPU?
Memory-mapped I/O assigns addresses to I/O registers from the main memory space, accessed using standard LOAD/STORE instructions.
Which I/O data transfer mode allows high-speed hardware data transfers directly between device and main memory without CPU intervention for each byte?
DMA hardware transfers blocks of data directly between I/O peripherals and RAM without CPU instruction execution per byte.
In DMA Cycle Stealing Mode, when does the DMA controller return control of the system bus to the CPU?
In cycle-stealing mode, the DMA controller typically transfers one bus word (or one bus cycle's worth of data) and then releases the bus so the CPU can use it.
A DMA controller transfers 100,000 bytes/s, and each DMA memory transfer occupies the memory bus for 1 microsecond. What percentage of one second of bus time is occupied by DMA transfers?
DMA occupies the bus for 100,000 $\times 1 microsecond = 0.1 second per second$, so the bus-time fraction is 0.1 = 10%.
Which 8085 microprocessor hardware interrupt is non-maskable and has the highest priority?
TRAP is the highest-priority non-maskable hardware interrupt in the 8085 architecture.