A TLB has access time 1 ns and hit ratio 0.98. Main memory access time is 50 ns. What is the Effective Memory Access Time (EMAT)?
$EMAT = T_{TLB} + T_{MM} + (1 - H_{TLB}) * T_{MM} = 1 + 50 + 0.02 * 50 = 51 + 1 = 52 ns.$
What hardware structure caches Virtual-to-Physical page address translations inside the MMU?
TLB is an associative hardware cache in the MMU that stores recent virtual-to-physical address translations.
A sequential row-major traversal of a 2D array of 8-byte double-precision elements is performed. Assume no conflict/capacity misses and a 32-byte cache block. What is the data-cache hit ratio after the first block is brought in?
A 32-byte block holds 32/8 = 4 double-precision elements. For sequential access, each block causes one compulsory miss followed by three hits, giving a steady-state hit ratio of 3/4 = 75%.
What is Thrashing in virtual memory systems?
Thrashing occurs when active processes' working sets exceed physical RAM, causing continuous page faulting.
How many 16K x 4 RAM chips are required to construct a 64K x 8 memory module?
Rows required = 64K / 16K = 4. Chips per row = 8 bits / 4 bits = 2. Total chips = 4 * 2 = 8 chips.