What occurs in a JK flip-flop when both J and K inputs are set to 1 under clock pulse?
When $J=1$ and $K=1$, the JK flip-flop complements its state on each clock pulse (toggle condition), eliminating the SR invalid state.
What is the total number of distinct states in a 4-bit binary counter?
An n-bit binary counter cycles through $2^n$ unique states. For $n = 4 bits, it counts through 2^4 = 16 states (0000$ to 1111).
What primary advantage does CMOS logic family offer over TTL logic family?
CMOS (Complementary Metal-Oxide-Semiconductor) technology consumes virtually zero static power, drawing current only during logic switching.
How does a Mealy finite state machine differ from a Moore state machine?
In a Mealy machine, output is a function of (Present State, Input). In a Moore machine, output depends strictly on (Present State).
Which logic condition is forbidden or invalid in a basic SR latch built with NOR gates?
For a NOR-based SR latch, setting $S=1$ and $R=1 forces both Q$ and Q' outputs to 0 simultaneously, violating complementation.