Question 111
[Q.11] In computer logic, an SR Flip-Flop enters an undefined/invalid state when:
Detailed Solution
S=1, R=1 causes both outputs Q and Q' to attempt to go LOW, resulting in an illegal/undefined state.
[Q.11] In computer logic, an SR Flip-Flop enters an undefined/invalid state when:
S=1, R=1 causes both outputs Q and Q' to attempt to go LOW, resulting in an illegal/undefined state.
[Q.12] What is the binary representation of the decimal number 43?
43 = 32 + 8 + 2 + $1 = 2^5 + 2^3 + 2^1 + 2^0$ = 101011_2.
[Q.13] A 4-bit binary ripple counter consists of 4 flip-flops. If the input clock frequency is 16 MHz, what is the output frequency of the final flip-flop?
Each flip-flop divides frequency by 2. For 4 flip-flops, output frequency = 16 MHz / $2^4$ = 16 / 16 = 1 MHz.
[Q.14] Which cache write policy updates both the cache and the main memory simultaneously on a write hit?
Write-Through writes data to both cache and underlying main memory at the same time.
[Q.15] What does EBCDIC stand for?
EBCDIC = Extended Binary Coded Decimal Interchange Code.