ISRO CSE 2014 PYQ

This question depends on the referenced sequential-circuit diagram. To verify the final state, the flip-flop types, clocking, input connections, and feedback paths must be read and the state transition repeated for four clock edges from Q1Q0 = 00. The diagram is not included in the text available here, so the supplied answer 11 cannot be independently confirmed and remains provisional.

The decomposition is dependency-preserving because A → B is contained in R1(A,B), and C → D is contained in R2(C,D). But R1 and R2 have no common attributes, so their natural join is a Cartesian product. It can create spurious tuples and cannot in general reconstruct the original relation losslessly. Hence it preserves the stated dependencies but is not guaranteed to be lossless.

A 70% statement about code coverage does not, by itself, determine the module’s operational reliability. If the intended textbook model assumes that the observed success probability 0.95 applies to the tested 70% and makes no guarantee about the untested 30%, then the common bounds are 0.70 $\times 0.95 = 0.665 as a lower estimate$ and 0.95 as an upper bound. Under that model the best option is “0.665 to 0.95,” not “at the most 0.95” alone. This conclusion depends on the simplified coverage model; code coverage is not generally equivalent to input-space reliability.

For RSA, $n = pq = 5\times 11 = 55$ and $\phi (n) = (5-1)(11-1) = 40$. The decryption exponent d is the multiplicative inverse of e modulo $\phi (n)$: 27d ≡ 1 (mod 40). Since 27$\times 3 = 81 = 2\times 40 + 1$,$d = 3$.

The required memory is $2^21$ bits = $2^18$ bytes = 256 KiB. Each 2K$\times 8 chip stores 2048 bytes$. Four chips in parallel provide a 32-bit (4-byte) word, so the number of word rows/banks is 256 KiB ÷ (2 KiB $\times 4 chips) = 32$. Selecting one of 32 banks requires a 5-to-32 decoder. The correct option is 5 to 32, not 4 to 16.