Question 1
Consider a 33MHz cpu based system. What is the number of wait states required if it is interfaced with a 60ns memory? Assume a maximum of 10ns delay for additional circuitry like buffering and decoding.
A wait state is an extra clock period inserted when the memory cannot complete an access within the processor's normal memory cycle. The CPU clock period is $T = 1/(33 \times 10^6) seconds \approx 30.30 ns$. The memory plus address-decoding/buffering delay is 60 + 10 = 70 ns. Two clock periods provide about 60.61 ns, which is insufficient. Three periods provide about 90.91 ns, which is sufficient. Therefore, one additional wait state is required (assuming the normal access window is two T-states).