How can a JK flip-flop be converted into a T flip-flop?
Tying J and K together (J = K = T) creates a T flip-flop: $T=0 holds (J=K=0)$ and $T=1 toggles (J=K=1)$.
A Master-Slave JK flip-flop is constructed using two JK flip-flops. If the propagation delay of each flip-flop is 15 ns, what is the total propagation delay of the Master-Slave flip-flop in ns?
In a Master-Slave flip-flop, the master samples during the HIGH clock period and the slave transfers to output on the falling edge. Output changes on the falling edge after the slave's delay of 15 ns.
What phenomenon occurs in an edge-triggered JK flip-flop if $J = 1$, $K = 1$, and the clock pulse width is much greater than the propagation delay of the flip-flop without edge-triggering?
When $J=1$ and $K=1$ with a level-triggered clock whose pulse width $t_p$ > $t_{pd}$, the output toggles multiple times unpredictably during a single clock pulse. This is the race-around condition.
Which method completely eliminates the race-around condition in JK flip-flops?
Edge-triggering or Master-Slave architecture restricts state changes to clock transitions, eliminating race-around.
In a flip-flop, the setup time is 4 ns and the hold time is 2 ns. If the clock edge arrives at time $t = 20 ns$, during which time interval (in ns) must the data input remain stable?
The data input must be stable from (t_clock - t_setup) to (t_clock + t_hold). Thus, from 20 - 4 = 16 ns to 20 + 2 = 22 ns.