What is the characteristic equation of a JK flip-flop?
The characteristic equation of a JK flip-flop is derived from its truth table: Q_next = J Q' + K' Q.
Which input condition causes an invalid/indeterminate state in an SR latch constructed using NOR gates?
For a NOR-based SR latch, setting $S = 1$ and $R = 1 forces both outputs Q$ and Q' to 0 simultaneously, violating the complementary output rule and causing race conditions upon removal.
For an SR latch constructed using NAND gates, which input combination produces the invalid/forbidden state?
For an active-LOW NAND-based S'R' latch, S'=0 and R'=0 forces both outputs Q and Q' to 1, leading to an invalid state.
In a T flip-flop, if $T = 1$, what is the next state Q_next?
When $T = 1$, the T flip-flop toggles its state on every clock pulse, so Q_next = Q' = NOT(Q).
A D flip-flop is constructed using a JK flip-flop by connecting the D input directly to J, and connecting K through an inverter. What is K in terms of D?
Setting $J = D$ and K = D' transforms the JK flip-flop into a D flip-flop, guaranteeing Q_next = D.