Which memory type offers the fastest access time and is used for constructing CPU Cache memory?
Static RAM (SRAM) is built using 6-transistor flip-flop circuits that retain data without needing periodic refresh cycles, providing ultra-fast access speeds suitable for Level 1/2/3 CPU caches.
Why does Dynamic RAM (DRAM) require periodic refreshing cycles?
DRAM cells store binary data as electrical charges inside single-transistor MOS capacitors. Because charge gradually leaks, refreshing circuits must periodically read and rewrite the charge.
In a 2-way Set-Associative Cache, how many cache lines are present in each cache set?
In an k-way set-associative cache, each set consists of exactly k cache blocks/lines. A 2-way set-associative cache contains 2 lines per set.
Which cache mapping technique allows a main memory block to be placed into ANY line in the cache?
Fully Associative Mapping provides maximum flexibility by permitting any main memory block to reside in any arbitrary cache block, eliminating conflict misses at the expense of complex tag comparators.
In Direct Cache Mapping, how is the target cache line index calculated for main memory block number B and total cache lines N?
Direct mapping maps main memory block B to a unique cache line index given by the modulo formula: Line_Index = B mod N.